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Freescale Semiconductor Technical Data
Document Number: MC33689 Rev. 7.0, 8/2006
System Basis Chip with LIN Transceiver
The 33689 is a SPI-controlled System Basis Chip (SBC) that combines many frequently used functions in an MCU-based system plus a Local Interconnect Network (LIN) transceiver. Applications include power window, mirror, and seat controls. The 33689 has a 5.0 V, 50 mA low dropout regulator with full protection and reporting features. The device provide full SPI-readable diagnostics and a selectable timing watchdog for detecting errant operation. The LIN transceiver waveshaping circuitry can be disabled for higher data rates. One 50 mA and two 150 mA high-side switches with output protection are available to drive inductive or resistive loads. The 150 mA switches can be pulse-width modulated (PWM). Two high-voltage inputs are available for contact monitoring or as external wake-up inputs. A current sense operational amplifier is available for load current monitoring. The 33689 has three operational modes: * Normal (all functions available) * Sleep (VDD OFF, wake-up via LIN bus or wake-up inputs) * Stop (VDD ON, wake-up via MCU, LIN bus, or wake-up inputs) Features * * * * * * * Full-Duplex SPI Interface at Frequencies up to 4.0 MHz LIN Transceiver Capable to 100 kbps with Waveshaping Capability 5.0 V Low Dropout Regulator Full Fault Detection and Protection One 50 mA and Two 150 mA Protected High-Side Switches Current Sense Operational Amplifier The 33689 is compatible with LIN 2.0 Specification Package. Pb-Free Packaging Designated by Suffix Code EW
VDD VPWR
33689D
SYSTEM BASIS CHIP WITH LIN
DWB SUFFIX EW SUFFIX (PB-FREE) 98ARH99137A 32-PIN SOICW
ORDERING INFORMATION
Device MC33689DDWB/R2 MCZ33689DEW/R2 -40C to 125C 32 SOICW Temperature Range (TA) Package
33689
VS1 VS2 VCC VDD WDC HS3 L1 L2
5.0 V
HS1 CS MCU SCK MOSI MISO SPI CS SCLK MOSI MISO INT RST IN OUT TXD RXD HS2 E+ EGND TGND AGND LIN
BUS
Figure 1. 33689 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2006. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VS1
5.0 V/50 mA Voltage Regulator Reset Control
VDD
RST
VS2
Window Watchdog
WDC IN MOSI
HS1
HS2 Pre-Driver HS3
SPI and Mode Control
MISO SCLK CS INT
VCC L1
Current Sense Op Amp
EE+ OUT TXD RXD
L2 VS1
LIN
LIN Physical Interface
GND
TGND
AGND
Figure 2. 33689 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
NC L1 NC L2 HS3 HS2 HS1 TGND TGND VS2 LIN GND VS1 NC VDD AGND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
TXD RXD
INT CS
MISO MOSI SCLK TGND TGND IN
RST WDC
E+ EOUT VCC
Figure 3. 33689 32-SOICW Pin Connections Table 1. 33689 32-SOICW Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Pin 1, 3, 14 2, 4 5-7 8, 9, 24, 25 10 11 12 13 15 16 17 18 19 20 21 Pin Name NC L1, L2 HS3 - HS1 TGND VS2 LIN GND VS1 VDD AGND VCC OUT EE+
WDC
Formal Name No Connect Level Inputs 1 and 2 High-Side Driver Outputs 3 through 1 Thermal Ground Voltage Supply 2 LIN Bus Ground Voltage Supply 1 5.0 V Regulator Output Analog Ground Power Supply In Amplifier Output Amplifier Inverted Input Amplifier Non-Inverted Input Watchdog Configuration (Active Low)
Pin Function N/A Input Output N/A Input Input / Output N/A Input Output N/A Input Output Input Input Reference
Definition No internal connection to these pins. Inputs from external switches or from logic circuitry. High-side (HS) drive power outputs. SPI-controlled for driving system loads. Thermal ground pins for the device. Supply pin for the high-side switches HS1, HS2, and HS3. Bidirectional pin that represents the single-wire bus transmitter and receiver. Electrical ground pin for the device. Supply pin for the 5.0 V regulator, the LIN physical interface, and the internal logic. Output of the 5.0 V regulator. Analog ground pin for voltage regulator and current sense operational amplifier. 5.0 V supply for the internal current sense operational amplifier. Output of the internal current sense operational amplifier. Inverted input of the internal current sense operational amplifier. Non-inverted input of the internal current sense operational amplifier. Configuration pin for the watchdog timer.
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PIN CONNECTIONS
Table 1. 33689 32-SOICW Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 19.
Pin 22 23 26 27 28 29 30 31 32 Pin Name
RST
Formal Name Reset Output (Active LOW) PWM Input Control Serial Data Clock Master Out Slave In Master In Slave Out Chip Select (Active LOW) Interrupt Output (Active LOW) Receiver Output Transmitter Input
Pin Function Output Input Input Input Output Input Output Output Input
Definition 5.0 V regulator and watchdog reset output pin. External input PWM control pin for high-side switches HS1 and HS2. Clock input for the SPI of the 33689. SPI data received by the 33689. SPI data sent to the MCU by the 33689. When CS is HIGH, pin is in the high-impedance state. SPI control chip select input pin. This output pin reports faults to the MCU when an enabled interrupt condition occurs. Receiver output of the LIN interface and reports the state of the bus voltage. Transmitter input of the LIN interface and controls the state of the bus output.
IN SCLK MOSI MISO
CS
INT
RXD TXD
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS VPWR Supply Voltage at VS1 and VS2 Continuous Transient (Load Dump) Supply Voltage at VDD and VCC Output Current at VDD Logic Input Voltage at MOSI, SCLK, CS, IN, and TXD Logic Output Voltage at MISO, INT, RST, and RXD Input Voltage at E+ and EInput Current at E+ and EOutput Voltage at OUT Output Current at OUT Input Voltage at L1 and L2 DC Input with a 33 k Resistor Transient Input with External Component (per ISO7637 Specification) (See Figure 4, page 6) Input / Output Voltage at LIN DC Voltage Transient Input Voltage with specified External Component (per ISO7637 Specification) (See Figure 4, page 6) DC Output Voltage at HS1 and HS2 Positive Negative DC Output Voltage at HS3 ESD Voltage, Human Body Model (1) GND Configured as Ground. TGND and AGND Configured as I/O Pins LIN, L1, and L2 All Other Pins ESD Voltage, Charge Device Model
(1)
Symbol
Value
Unit
V VSUPDC VSUPTR VDD IDD VINLOG VOUTLOG VE+ / VEIE+ / IEVOUT IOUT VLXDC VLXTR - 0.3 to 27 40 - 0.3 to 5.5 Internally Limited - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 0.3 to 7.0 20 - 0.3 to VCC + 0.33 20 V A V V V mA V mA V -18 to 40 100 V VBUSDC VBUSTR VHS+ VHSVHS3 VESD1 -18 to 40 -150 to 100 V VVS2 + 0.3 Internally Clamped - 0.3 to VVS2 + 0.3 V V
4000 2000 VESD2 750 500 V
Corner Pins (Pins 1, 16, 17, and 32) All other Pins (Pins 2 - 15 and 18 - 31)
Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Charge Device Model, Robotic (CZAP = 4.0 pF).
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
Table 2. Maximum Ratings(continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Thermal Resistance, Junction-to-Ambient Peak Package Reflow Temperature During Solder Mounting (2) TA TJ TSTG RJA TSOLDER - 40 to 125 - 40 to 150 - 55 to 165 80 240 C C/ W C C Symbol Value Unit
Notes 2. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause permanent damage to the device.
33689D 1.0 nF LIN, L1, L2 10 k GND TGND AGND Transient Pulse Generator (Note) GND
Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.
Figure 4. ISO 7637 Test Setup for LIN, L1, and L2 Pins
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 18 V, - 40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic VS1 AND VS2 INPUT PINS (DEVICE POWER SUPPLY) Supply Input Voltage Nominal DC Load Dump Jump Start
(3)
Symbol
Min
Typ
Max
Unit
V VSUP VSUPLD VSUPJS ISUP(NORM) ISLEEP ISTOP 5.5 -- -- -- -- -- 18 40 27
Supply Input Current (4) Normal Mode, IOUT at VDD = 10 mA, LIN Recessive State Sleep Mode, VDD OFF, VSUP 13.5 V Stop Mode, VDD ON with IOUT < 100 A, VSUP 13.5 V Input Threshold Voltage (Normal Mode, Interrupt Generated) Fall Early Warning, Bit VSUV Set Overvoltage Warning, Bit VSOV Set Hysteresis (5) VSUV Flag VSOV Flag VDD OUTPUT PIN (EXTERNAL 5.0 V OUTPUT FOR MCU USE) (6) Output Voltage IDD from 2.0 mA to 50 mA, 5.5 V < VSUP < 27 V Dropout Voltage (7) IDD = 50 mA Output Current Limitation (8) Overtemperature Pre-warning (Junction) Normal Mode, Interrupt Generated, Bit VDDT Set Thermal Shutdown (Junction) Normal Mode TSD 165 170 -- IDD TPRE 120 135 160 C VDDDROP -- 50 0.1 120 0.2 200 mA C VDDOUT 4.75 5.0 5.25 V V VSUVEW VSOVW VHYS -- -- 1.0 220 -- -- V mV 5.7 18 6.1 19.75 6.6 20.5 -- -- -- 5.0 35 60 8.0 45 75 mA A A V
Notes 3. Device is fully functional. All features are operating. An overtemperature fault may occur. 4. Total current (IVS1 + IVS2) at VS1 and VS2 pins is measured at the ground pins. 5. 6. 7. 8. Parameter guaranteed by design; however, it is not production tested. Specification with external capacitor 2.0 F < C < 10 F and 200 m ESR 10 . Normal mode. Low ESR electrolytic capacitor values up to 47 F can be used. Measured when the voltage has dropped 100 mV below its nominal value. Internally limited. Total 5.0 V regulator current. A 5.0 mA current for the Current Sense Operational Amplifier operation is included. Digital outputs are supplied from VDD.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, - 40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic VDD OUTPUT PIN (5.0 V OUTPUT FOR MCU USE) (CONTINUED) Temperature Threshold Difference Normal Mode (TSD - TPRE) VSUP Range for Reset Active 0.5 V < VDD < VDD (V RSTTH) Line Regulation 5.5 V < VSUP < 27 V, IDD = 10 mA Load Regulation 1.0 mA < IDD < 50 mA VDD OUTPUT PIN IN STOP MODE Output Voltage (10) IDD 2.0 mA Output Current Capability (11) Line Regulation 5.5 V < VSUP < 27 V, IDD = 2.0 mA Load Regulation 1.0 mA < IDD < 5.0 mA
RST OUTPUT PIN IN NORMAL AND STOP MODES
(9)
Symbol
Min
Typ
Max
Unit
TDIFF 20 VSUPR 4.0 VLR1 -- VLD1 -- 10 150 20 150 -- -- 30 40
C
V
mV
mV
VDDS 4.75 IDDS VLRS -- VLDS -- 40 150 10 100 4.0 5.0 8.0 5.25 14
V
mA mV
mV
Reset Threshold Voltage Low-Level Output Voltage IO = 1.5 mA, 4.5 V < VSUP < 27 V High-Level Output Current 0.0 V < VOUT < 0.7 VDD Reset Pulldown Current Internally Limited, VDD < 4.0 V, VRST = 4.6 V IN INPUT PIN Low-Level Input Voltage High-Level Input Voltage Input Current 0.0 V < VIN < VDD
V RSTTH VOL
4.5
4.7
VDD - 0.2 0.9
V V
0.0 IOH -- IPDRST 1.5
--
A - 275 -- mA -- 8.0
VIL VIH IIN
- 0.3 0.7 VDD -10
-- --
0.3 VDD VDD + 0.3 10
V V A
--
Notes 9. Specification with external capacitor 2.0 F < C < 10 F and 200 m ESR 10 . Normal mode. Low ESR electrolytic capacitor values up to 47 F can be used. 10. When switching from Normal mode to Stop mode or from Stop mode to Normal mode, the voltage can vary within the output voltage specification. 11. When IDD is above IDDS, the 33689 enters the Reset mode.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, - 40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic MISO SPI OUTPUT PIN Low-Level Output Voltage I OUT = 1.5 mA High-Level Output Voltage I OUT = 250 A Tri-Stated MISO Output Leakage Current 0.0 V < VMISO < VDD MOSI, SCLK, CS SPI INPUT PINS Low-Level Input Voltage High-Level Input Voltage Pullup Input Current on CS VCS = 4.0 V MOSI, SCLK Input Current 0.0 V < VIN < VDD
INT OUTPUT PIN
Symbol
Min
Typ
Max
Unit
VOL 0.0 VOH VDD - 0.9 IHZ - 2.0 -- 2.0 -- VDD -- 1.0
V
V A
VIL VIH IPUCS
- 0.3 0.7 VDD -100
-- --
0.3 VDD VDD + 0.3 - 20
V V A
--
IIN -10 -- 10
A
Low-Level Output Voltage IO = 1.5 mA High-Level Output Voltage IO = - 250 A
WDC PIN
VOL 0.0 VOH VDD - 0.9 -- VDD -- 0.9
V
V
External Resistor Range HS1 AND HS2 HIGH-SIDE OUTPUT PINS Output Clamp Voltage I OUT = -100 mA Output Drain-to-Source ON Resistance TA = 25C, I OUT -150 mA TA = 125C, I OUT -150 mA TA = 125C, I OUT -120 mA Output Current Limitation Overtemperature Shutdown Output Leakage Current
(12)
R EXT
10
--
100
k
VCL - 6.0 RDS(ON) -- -- -- ILIM TOTSD ILEAK 300 155 -- 2.0 -- 3.0 430 -- -- 2.5 4.5 4.0 600 190 10 -- --
V
mA C A
Notes 12. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI Register. Refer to description on page 26.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, - 40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic HS3 HIGH-SIDE OUTPUT PIN Output Drain-to-Source ON Resistance TA = 25C, I OUT - 50 mA TA = 125C, I OUT - 50 mA TA = 125C, I OUT - 30 mA Output Current Limitation Overtemperature Shutdown (13) Output Leakage Current OUT, E+, AND E- PINS AT CURRENT SENSE OPERATIONAL AMPLIFIER Input Voltage - Rail-to-Rail at E+ and EOutput Voltage Range at OUT With 1.0 mA Output Load Current With 5.0 mA Output Load Current Input Bias Current Input Offset Voltage Input Offset Current L1 AND L2 INPUT PINS Low-Voltage Detection Input Threshold Voltage 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V High-Voltage Detection Input Threshold Voltage 5.5 V < VSUP < 6.0 V 6.0 V < VSUP < 18 V 18 V < VSUP < 27 V Input Hysteresis 5.5 V < VSUP < 27 V Input Current - 0.2 V < VIN < 40 V IIN -10 -- 10 VHYS 0.5 -- 1.3 A VTHH 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.5 4.7 V VTHL 2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.5 3.7 V V IB V IO IO VIMC VOUT 0.1 0.3 -- -15 -100 -- -- -- -- -- VCC - 0.1 VCC - 0.3 250 15 100 nA mV nA - 0.1 -- VCC + 0.1 V V ILIM TOTSD ILEAK RDS(ON) -- -- -- 60 155 -- 5.5 -- 10 100 -- -- 7.0 10 14 200 190 10 mA C A Symbol Min Typ Max Unit
Notes 13. When overtemperature occurs, switch is turned off and latched off. Flag is set in SPI Register. Refer to description on page 26.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, - 40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic RXD OUTPUT PIN (LIN PHYSICAL LAYER) Low-Level Output Voltage I OUT 1.5 mA High-Level Output Voltage I OUT 250 A TXD INPUT PIN (LIN PHYSICAL LAYER) Low-Level Input Voltage High-Level Input Voltage Input Hysteresis Pullup Current Source 1.0 V < VTXD < 3.5 V LIN PHYSICAL LAYER, TRANSCEIVER Transceiver Output Voltage Dominant State, TXD LOW, External Bus Pullup 500 Recessive State, TXD HIGH, I OUT = 1.0 A Pullup Resistor to VSUP In Normal Mode and in Sleep and Stop Modes When Not Disabled by SPI Pullup Current Source In Sleep and Stop Modes When Pullup Disabled by SPI Output Current Shutdown Threshold Leakage Output Current to GND VS1 and VS2 Disconnected, VLIN = 18 V Recessive State, 8.0 V < VSUP < 18 V, 8.0 V < VLIN < 18 V GND Disconnected, VGND = VSUP , VLIN = -18 V LIN PHYSICAL LAYER, RECEIVER Receiver Input Threshold Voltage Dominant State, TXD HIGH, RXD LOW Recessive State, TXD HIGH, RXD HIGH Center (VBUSDOM - VBUSREC) / 2 Hysteresis (VBUSDOM - VBUSREC) Bus Wake-Up Threshold VBUSDOM VBUSREC VBUSCNT VBUSHYS VBUSWU 0.0 0.6 0.475 -- -- -- -- 0.5 -- 0.5 0.4 1.0 0.525 0.175 -- VSUP VSUP IOUTSD IBUSLEAK -- 0.0 -1.0 1.0 3.0 -- 10 20 1.0 A A mA IPULIN -- 50 1.3 75 -- 150 mA VLINDOM VLINREC RPU 20 30 47 A -- VSUP -1.0 -- -- 1.4 -- k V VIL VIH VINHYS IPUTXD -100 -- - 20 -- 3.5 50 -- -- 145 1.5 -- 300 V V mV A VOH 3.75 -- 5.25 VOL 0.0 -- 0.9 V V Symbol Min Typ Max Unit
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V VSUP 18 V, - 40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic SPI INTERFACE CHARACTERISTICS SPI Operation Frequency SCLK Clock Period SCLK Clock High Time SCLK Clock Low Time Falling Edge of CS to Rising Edge of SCLK Falling Edge of SCLK to CS Rising Edge MOSI to Falling Edge of SCLK (Data Setup Time) Falling Edge of SCLK to MOSI (Data Hold Time) MISO Rise Time (14) CL = 220 pF MISO Fall Time (14) CL = 220 pF Time from Falling or Rising Edge of CS to: (14) MISO Low Impedance (Enable) MISO High Impedance (Disable) Time from Rising Edge of SCLK to MISO Data Valid (14) 0.2 VDD MISO 0.8 VDD, CL = 100 pF
RST OUTPUT PIN IN NORMAL AND STOP MODES
Symbol
Min
Typ
Max
Unit
fSPI
0.25 250 125 125 100 100 40 40
-- -- -- -- -- -- -- --
4.0 N/A N/A N/A N/A N/A N/A N/A
MHz ns ns ns ns ns ns ns ns
t PSCLK t WSCLKH t WSCLKL t LEAD t LAG t SI (SU) t SI (HOLD) t RSO
--
25
50 ns
t FSO
-- 25 50
ns
t SO (EN) t SO (DIS) t VALID
0.0 0.0
-- --
50 50 ns
0.0
--
50
Reset Duration After VDD HIGH
WDC PIN
t DURRST
0.65
1.0
1.35
ms
Watchdog Period Accuracy Using an External Resistor (Excluding Resistor Tolerances) (15) Watchdog Time Period (15) 10 k External Resistor 100 k External Resistor No External Resistor, WDC Open, Normal Mode
ACC WDC
-15
--
15
% ms
t WDC
-- -- 107 10.558 99.748 160 -- -- 215
Notes 14. Parameter guaranteed by design; however, it is not production tested. 15. Watchdog time period calculation formula: t WDC = 0.991 * R + 0.648 (R in k and t WDC in ms).
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, - 40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic CURRENT SENSE OPERATIONAL AMPLIFIER Supply Voltage Rejection Ratio (16) Common Mode Rejection Ratio (16) Gain Bandwidth (16) Output Slew Rate Phase Margin Open Loop Gain
(16)
Symbol
Min
Typ
Max
Unit
SVR CMR GBP SR PHMO OLG
60 70 1.0 0.5 40 --
-- -- -- -- -- 85
-- -- -- -- -- --
dB dB MHz V/s deg. dB
L1 AND L2 INPUT PINS Wake-Up Filter Time (16) STATE MACHINE TIMING Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command) and Stop Mode Activation (16) Minimum Watchdog Period No Watchdog Selected Maximum Watchdog Period Interrupt Low-Level Duration Internal Oscillator Frequency Accuracy (All Modes, for Information Only) Normal Request Mode Time-Out (Normal Request Mode) Delay Between SPI Command and HS1 or HS2 Turn On (17), (18) Normal Mode, VSUP > 9.0 V, VHS 0.2 VVS2 Delay Between SPI Command and HS1 or HS2 Turn Off (17), (18) Normal Mode, VSUP > 9.0 V, VHS 0.8 VVS2 Delay Between SPI Command and HS3 Turn On (17), (19) Normal Mode, VSUP > 9.0 V, VHS 0.2 VVS2 Delay Between SPI Command and HS3 Turn Off (17), (19) Normal Mode, VSUP > 9.0 V, VHS 0.8 VVS2 Delay Between Normal Request and Normal Mode After a Watchdog Trigger Command (Normal Request Mode) (16) Delay Between CS Wake-Up (CS LOW to HIGH) in Stop Mode and: Normal Request Mode, VDD ON and RST HIGH First Accepted SPI Command Delay Between Interrupt Pulse in Stop Mode After Wake-Up and First Accepted SPI Command Minimum Time Between Rising and Falling Edge on the CS s 1.4 6.0 12 -- -- -- 10 -- 150 5.0 30 50 13 35 205 s % ms s -- -- 20 s -- -- 20 s -- -- 20 s -- -- 15 20 30 s
t WUF
8.0
20
38
s
t STOP
s
t INT fOSC t NRTOUT t SHSON
7.0 - 35 97
t SHSOFF
tSHSON
tSHSOFF
t SNR2N
7.0
t WUCS t WUSPI t S1STSPI t 2CS
15 90 30 15
40 -- -- --
80 N/A N/A -- s s
Notes 16. Parameter guaranteed by design; however, it is not production tested. 17. When IN input is set to HIGH, delay starts at falling edge of clock cycle #8 of the SPI command and start of device activation/deactivation. 30 mA load on high-side switches. Excluding rise or fall time due to external load. 18. When IN is used to control the high-side switches, delays are measured between IN and HS1 or HS2 ON / OFF. 30 mA load on high-side switches, excluding rise or fall time due to external load. 19. Delay between turn on or turn off command and HS ON or HS OFF, excluding rise or fall time due to external load.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, - 40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min
(20)
Typ
Max
Unit
LIN PHYSICAL LAYER: BUS DRIVER TIMING CHARACTERISTICS FOR NORMAL SLEW RATE Propagation Delay TXD to LIN (21) Dominant State Minimum Threshold (50% TXD to 58.1% VSUP) Dominant State Maximum Threshold (50% TXD to 28.4% VSUP) Recessive State Minimum Threshold (50% TXD to 42.2% VSUP) Recessive State Maximum Threshold (50% TXD to 74.4% VSUP) Propagation Delay Symmetry
s
t DOMMIN t DOMMAX t RECMIN t RECMAX
dt1s dt2s
-- -- -- --
-- -- -- --
50 50 50 50 s
t DOMMIN - t RECMAX t DOMMAX - t RECMIN
-10.44 --
(20)
-- --
-- 11
LIN PHYSICAL LAYER: BUS DRIVER TIMING CHARACTERISTICS FOR SLOW SLEW RATE Propagation Delay TXD to LIN (22) Dominant State Minimum Threshold (50% TXD to 61.6% VSUP) Dominant State Maximum Threshold (50% TXD to 25.1% VSUP) Recessive State Minimum Threshold (50% TXD to 38.9% VSUP) Recessive State Maximum Threshold (50% TXD to 77.8% VSUP) Propagation Delay Symmetry
s
t DOMMIN t DOMMAX t RECMIN t RECMAX
dt1s dt2s
-- -- -- --
-- -- -- --
100 100 100 100 s
t DOMMIN - t RECMAX t DOMMAX - t RECMIN
LIN PHYSICAL LAYER: BUS DRIVER FAST SLEW RATE LIN High Slew Rate (Programming Mode) LIN PHYSICAL LAYER, TRANSCEIVER Output Current Shutdown Delay (23)
- 22 --
-- --
-- 23
dv/dt Fast
--
13
--
V/s
t OUTDLY
--
10
--
s
Notes 20. 7.0 V < VSUP < 18 V, bus load C0 and R0 1.0 nF/1.0 k, 6.8 nF / 660 , 10 nF / 500 . 50% of TXD signal to LIN signal threshold. See Figure 5, page 16. 21. See Figure 7, page 17. 22. See Figure 8, page 17. 23. Parameter guaranteed by design; however, it is not production tested.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V VSUP 18 V, - 40C TA 125C, GND = 0.0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit LIN PHYSICAL LAYER: RECEIVER CHARACTERISTICS AND WAKE-UP TIMINGS Propagation Delay LIN to RXD (24) Dominant State (LIN LOW to RXD LOW) Recessive State (LIN HIGH to RXD HIGH) Symmetry (t RDOM - t RREC) Bus Wake-Up Deglitcher (Sleep and Stop Modes) (25) Bus Wake-Up Event Reported From Sleep Mode
(26)
s
t RDOM t RREC t RSYM t PROPWL t WU t WU
-- -- - 2.0 30
3.0 3.0 -- 70
6.0 6.0 2.0 90 s s
-- --
30 20
-- --
From Stop Mode (27)
Notes 24. Measured between LIN signal threshold VINL or VINH and 50% of RXD signal. 25. See Figures 9 and 10, page 18. 26. t WU is typically 2 internal clock cycles after a LIN rising edge is detected. In Sleep Mode, the measurement is done without a capacitor connected to the regulator. The delay is measured between the VSUP/2 rising edge of the LIN bus and when VDD reaches 3.0 V. The VDD rise time is strongly dependent upon the decoupling capacitor at VDD pin. See Figure 9, page 18. 27.
t WU is typically 2 internal clock cycles after a LIN rising edge is detected. In Stop Mode, the delay is measured between the VSUP/2 rising edge of the LIN bus and the falling edge of the INT pin. See Figure 10, page 18.
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TIMING DIAGRAMS
VPWR 33689 VS1/VS2 TXD RXD GND
R0/C0 Combinations: 1.0 k/1.0 nF 660 /6.8 nF 500 /10 nF
R0
LIN TGND AGND
C0
Figure 5. Test Circuit for Timing Measurements
t PSCLK
CS
t LEAD t WSCLKH t LAG
SCLK
t WSCLKL t SI(SU) t SI(HOLD)
MOSI
Undefined
t VALID t SO(EN)
DI 0
Don't Care
DI 7
Don't Care
t SO(DIS)
MISO
DO 0
DO 7
Note Incoming data at MOSI pin is sampled by the 33689 at SCLK falling edge. Outgoing data at MISO is set by the 33689 at SCLK rising edge (after tVALID delay time).
Figure 6. SPI Timing Characteristics
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
TXD Recessive State
VLINREC 58.1% VSUP
t RECMAX
74.4% VSUP
t DOMMIN
LIN 40% VSUP 28.4% VSUP 60% VSUP 42.2% VSUP
t DOMMAX
Dominant State
t RECMIN
RXD t RDOM tRREC
Figure 7. Timing Characteristics for Normal LIN Output Slew Rate
TXD Recessive State
VLINREC 61.6% VSUP
tRECMAX
77.8% VSUP 60% VSUP 38.9% VSUP
t DOMMIN
40% VSUP LIN 25.1% VSUP
t DOMMAX
Dominant State
tRECMIN
RXD t RDOM t RREC
Figure 8. Timing Characteristics for Slow LIN Output Slew Rate
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS
Recessive State VLINREC LIN 0.4 VSUP Dominant Level VDD
Recessive State VLINREC LIN 0.4 VSUP Dominant State
INT
t PROPWL
t WU
t PROPWL
t WU
Figure 9. LIN Bus Wake-Up Behavior, Sleep Mode
Figure 10. LIN Bus Wake-Up Behavior, Stop Mode
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
A System Basis Chip (SBC) is a monolithic IC combining many functions found in standard microcontroller-based systems; e.g., power management, communication interface, system protection, and diagnostics. The 33689 is a SPI-controlled SBC combining many functions with a LIN transceiver for slave node applications. The 33689 has a 5.0 V, 50 mA regulator with undervoltage reset, output current limiting, overtemperature pre-warning, and thermal shutdown. An externally selectable timing Window Watchdog is also included. The LIN transceiver has waveshaping that can be disabled when high data rates are warranted. A single 50 mA and two 150 mA fully protected high-side switches with output clamping are available for switching inductive or resistive loads. The 150 mA switches are PWM capable. Two high-voltage inputs can be used to monitor switches or provide external wake-up. An internal current sense operational amplifier is available for load current monitoring.
FUNCTIONAL PIN DESCRIPTION LEVEL 1 AND LEVEL 2 INPUT PINS (L1 AND L2)
These pins are used to sense external switches and to wake up the 33689 from Sleep or Stop mode. During Normal mode, the state of these pins can be read through the SPI Register. (Refer to the section entitled SPI Interface and Register Description on page 24 for information on the SPI Register.) battery. The 33689 can operate from 4.5 V and under the jump start condition at 27 V DC. Device functionality is guaranteed down to 4.5 V at VS1 and VS2 pins. These pins sustain standard automotive voltage conditions such as load dump at 40 V.
LIN BUS PIN (LIN)
The LIN pin represents the single-wire bus transmitter and receiver. It is suited for automotive bus systems and is based on the LIN bus specification.
HIGH-SIDE DRIVER OUTPUT PINS 1 AND 2 (HS1 AND HS2)
These two high-side switches are able to drive loads such as relays or lamps. They are protected against overcurrent and overtemperature and include internal clamp circuitry for inductive load protection. Switch control is done through selecting the correct bit in the SPI Register. HS1 and HS2 can be PWM-ed if required through the IN input pin. The internal circuitry that drives both high-side switches is an AND function between the SPI bit HS1 (or HS2) and the IN input pin. If no PWM control is required, the IN pin must be connected to the VDD pin.
VOLTAGE SOURCE PIN (VDD)
The VDD pin is the 5.0 V supply pin for the MCU and the current sense operational amplifier.
CURRENT SENSE OPERATIONAL AMPLIFIER PINS (E+, E- , VCC, AND OUT)
These are the pins of the single-supply current sense operational amplifier. * The E+ and the E- input pins are the non-inverting and inverting inputs of the current sense operational amplifier, respectively. * The OUT pin is the output pin of the current sense operational amplifier. * The VCC pin is the + 5.0 V single-supply connection for the current sense operational amplifier. The current sense operational amplifier is enabled in Normal mode only.
HIGH-SIDE DRIVER OUTPUT PIN 3 (HS3)
This high-side switch can be used to drive small lamps, Hall sensors, or switch pullup resistors. Control is done through the SPI Register only. No direct PWM control is possible on this pin. This high-side switch features current limit to protect it against overcurrent and short circuit conditions. It is also protected against overtemperature.
WATCHDOG CONFIGURATION PIN (WDC)
The WDC pin is the configuration pin for the internal watchdog. A resistor is connected to this pin. The resistor value defines the watchdog period. If the pin is left open, the watchdog period is fixed to its default value (150 ms typical). If no watchdog function is required, the WDC pin must be connected to GND.
VOLTAGE SUPPLY PINS 1 AND 2 (VS1 AND VS2)
The 33689 is supplied from a battery line or other supply source through the VS1 and VS2 pins. An external diode is required to protect against negative transients and reverse
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
RESET OUTPUT PIN (RST)
The RST pin is the 5.0 V regulator and Watchdog reset output pin.
PWM INPUT CONTROL PIN (IN)
The IN pin is the external PWM control pin for the HS1 and HS2 high-side switches.
Voltage regulator temperature pre-warning HS1, HS2, or HS3 thermal shutdown VS1 or VS2 overvoltage (20 V typical) VS1 or VS2 undervoltage (6.0 V typical) If an interrupt is generated, then when the next SPI read operation is performed bit D7 in the SPI Register will be set to logic [1] and bits D6 : D0 will report the interrupt source. In cases of wake-up from the Stop mode, INT is set LOW in order to signal to the MCU that a wake-up event from the L1, L2, or LIN bus pin has occurred.
* * * *
SERIAL DATA CLOCK PIN (SCLK)
The SCLK pin is the SPI clock input pin. MISO data changes on the negative transition of the SCLK. MOSI is sampled on the positive edge of the SCLK.
RECEIVER OUTPUT PIN (RXD)
The RXD pin is the receiver output of the LIN interface and reports the state of the bus voltage (RXD LOW when LIN bus is dominant, RXD HIGH when LIN bus is recessive).
MASTER OUT SLAVE IN PIN (MOSI)
The MOSI pin receives SPI data from the MCU. This data input is sampled on the positive edge of SCLK.
TRANSMITTER INPUT PIN (TXD)
The TXD pin is the transmitter input of the LIN interface and controls the state of the bus output (dominant when TXD is LOW, recessive when TXD is HIGH).
MASTER IN SLAVE OUT PIN (MISO)
The MISO pin sends data to an SPI-enabled MCU. Data on this output pin changes on the negative edge of the SCLK. When CS is HIGH, this pin enters the high-impedance state.
GROUND PINS (GND, TGND, AND AGND)
The 33689 has three different types of ground pins. * The GND pin is the electrical ground pin for the device. * The AGND is the analog ground pin for the voltage regulator and current sense operational amplifier. * The four TGND pins are the thermal ground pins for the device. Important The GND, the AGND, and the four TGND pins must be connected together to a ground external to the 33689.
CHIP SELECT PIN (CS)
The CS pin is the chip select input pin for SPI use. When this signal is high, SPI signals are ignored. Asserting this pin LOW starts an SPI transaction. The transaction is completed when this signal returns HIGH.
INTERRUPT OUTPUT PIN (INT)
The INT pin is used to report 33689 faults to the MCU. Interrupt pulses are generated for:
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION WINDOW WATCHDOG
The window watchdog can be configured using an external resistor at WDC pin. The watchdog is cleared through MODE1 and MODE2 bit in the SPI Register (refer to Table 2, page 24; also refer to the section entitled Functional Pin Description on page 19. A watchdog clear is only allowed in the open window (see Figure 1). If the watchdog is cleared in the closed window or has not been cleared at the end of the open window, the watchdog will generate a reset on the RST pin and reset the whole device. Note The watchdog clear in Normal request mode (150 ms) (first watchdog clear) has no window.
Window Closed. No Watchdog Clear Allowed Window Open for Watchdog Clear
the device. The output of the regulator is also connected to the VDD pin to provide the 5.0 V to the microcontroller. Current Limit (Overcurrent) Protection The voltage regulator has current limit to protect the device against overcurrent and short circuit conditions. Overtemperature Protection The voltage regulator also features overtemperature protection that has an overtemperature warning (Interrupt VDDT) and an overtemperature shutdown. Stop Mode During Stop mode, the Stop mode regulator supplies a regulated output voltage. The Stop mode regulator has a limited output current capability. Sleep Mode
t WDC * 50%
t WDC * 50% Watchdog Period t WDC
In Sleep mode, the voltage regulator external VDD is turned off.
VDD VOLTAGE REGULATOR TEMPERATURE PREWARNING
Figure 1. Window Watchdog Operation Window Watchdog Configuration If the WDC pin is left open, the default watchdog period is selected (typ. 150 ms). If no watchdog function is required, the WDC pin must be connected to GND. The watchdog timer's period is calculated using the following formula: t WDC = 0.991 * R +0.648 (with R in k and t WDC in ms). VDD voltage regulator temperature prewarning (VDDT) is generated if the voltage regulator temperature is above the TPRE threshold. It will set the VDDT bit in the SPI Register and an interrupt will be initiated. The VDDT bit remains set as long as the error condition is present. During Sleep and Stop modes the VDD voltage regulator temperature prewarning circuitry is disabled.
HIGH-SIDE SWITCH THERMAL SHUTDOWN
The high-side switch thermal shutdown HSST is generated if one of the high-side switches HS1 : HS3 is above the HSST threshold. It will shutdown all high-side switches and set the HSST flag in the SPI Register, and an interrupt will be initiated. The HSST bit remains set as long as the error condition is present. During Sleep and Stop modes the highside switch thermal shutdown circuitry is disabled.
VDD VOLTAGE REGULATOR
The 33689 chip contains a low-power, low dropout voltage regulator to provide internal power and external power for the MCU. The on-chip regulator consist of two elements, the main voltage regulator and the low-voltage reset circuit. The VDD regulator accepts an unregulated input supply and provides a regulated VDD supply to all digital sections of
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
As described below and depicted in Figure 1 below and Table 1 on page 23, the 33689 has three operational modes: Normal, Sleep, and Stop. Operational modes are controlled by MODE1 and MODE2 bits in the SPI Register (refer to Logic Commands and Registers on page 24). In additional, there are two transitional modes: Reset and Normal Request.
RESET MODE
At power up, the 33689 switches automatically to Reset Mode for 1 ms if VDD goes high. If VDD stays low, after 150 ms the 33689 goes in Sleep Mode.
NORMAL REQUEST MODE
Before entering in Normal Request Mode, the 33689 stays for 1 ms in Reset Mode. In this mode, the LIN bus can transmit and receive information.
VDD LOW (150 ms) Expired & VSUV Bit = Logic [0] VDD HIGH & Reset Counter (1.0 ms) Expired & Watchdog Not Selected VDD HIGH & Reset Counter (1.0 ms) Expired & Watchdog Selected
Reset
33689 Power-Up VDD LOW OR (Normal Request Timeout Occurs [150 ms] & Watchdog Selected)
Normal Request
Watchdog Trigger
Normal
Wake-Up & Watchdog Selected Wake-Up & Watchdog Not Selected Sleep Command VDD LOW OR (Watchdog Fail & Watchdog Selected) Stop Command
Power Down
VDD LOW Wake-Up
Stop Sleep
Legend
Watchdog Selected: External resistor between WDC pin and GND or WDC pin open. Watchdog Not Selected: WDC pin connected to GND. Watchdog Fail: Watchdog trigger occurs in closed window or no SPI Watchdog trigger command. Stop Command: SPI stop command. Sleep Command: SPI sleep request followed by SPI sleep command. Wake-Up: L1 or L2 state change or LIN bus wake-up or CS rising edge.
Figure 1. 33689 Modes State Diagram
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
NORMAL MODE
In Normal Mode, the 33689 has slew rate and timing compatible with the LIN protocol specification. The LIN bus can transmit and receive information. The VDD regulator is ON and the watchdog function can be enabled.
Entering Sleep Mode First and second SPI commands (with bit D6 = 1, D7 = 1, D5 = 0 or 1, D1 = 0, and D0 = 0) 11x00000 must be sent. Entering Stop Mode First and second SPI commands (with bit D6 = 1, D7 = 1, D5 = 0 or 1, D1 = 0, and D0 = 1) 11x00001 must be sent. Sleep or Stop modes are entered after the second SPI command. Register bit D5 must be set accordingly.
SLEEP AND STOP MODE
To safely enter Sleep or Stop modes and to ensure that these modes are not inadvertently entered due to noise issues during SPI transmission, a dedicated sequence must be sent twice: data with the bits controlling the LIN bus and the device mode. Table 1. Operational Modes and Associated Functions
Device Mode VDD Voltage Regulator VDD: ON Reset Wake-Up Capabilities N/A
RST Output
Watchdog Function Disabled
HS1, HS2, HS3 OFF
LIN Interface Recessive only
Operational Amplifier Not active
LOW for 1.0 ms typical, then HIGH (if VDD above threshold) HIGH. Active LOW if VDD undervoltage occurs and if Normal Request timeout (if Watchdog enabled) HIGH. Active LOW if VDD undervoltage occurs or if Watchdog fail (if Watchdog enabled) Normally HIGH. Active LOW if VDD undervoltage occurs LOW. Go to HIGH after Wake-Up and VDD within specification
VDD: ON
N/A
150 ms timeout if Watchdog enabled
ON or OFF
Transmit and receive
Not active
Normal Request
VDD: ON
N/A
Window Watchdog if enabled
ON or OFF
Transmit and receive
Active
Normal
Stop
VDD: ON (Limited current capability)
LIN and state change on L1:L2 inputs
Disabled
OFF
Recessive state with Wake capability
Not active
Sleep
VDD: OFF (Set to 5.0 V after Wake-Up to enter Normal Request)
LIN and state change on L1:L2 inputs
Disabled
OFF
Recessive state with Wake capability
Not active
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS SPI INTERFACE AND REGISTER DESCRIPTION
As shown in Figure 2, the SPI is an 8-bit SPI. All data is sent as bytes. The MSB, D7, is sent first. The minimum time between two rising edges on the CS pin is 15 s. During an SPI data communication, the state of MISO reports the state of the 33689 at time of a CS HIGH-to-LOW transition. The status flags are latched at a CS HIGH-to-LOW transition.
Bit7 MISO D7
Bit6 D6
Bit5 D5
Bit4 D4
Bit3 D3
Bit2 D2
Bit1 D1
Bit0 D0 MOSI
Figure 2. Data Format Description The following tables describe the SPI Register bits, showing reset values and reset conditions. Table 2. SPI Register Overview
Read / Write Information Write Read MSB D7 LINSL2 INTSRC (1) D6 LINSL1 LINWU or LINFAIL 0 D5 LIN-PU VSOV D4 HS3 VSUV or BATFAIL(2) 0 Bits D3 HS2 VDDT D2 HS1 HSST D1 MODE2 L2 LSB D0 MODE1 L1
Write Reset Value Write Reset Condition
0
0
0
0
--
--
POR, RESET
POR, RESET
POR
POR, RESET
POR, RESET
POR, RESET
--
--
Notes 1. D7 signals interrupt source. After interrupt occurs, if D7 is a logic [1] D6 : D0 indicate the interrupt source. If D7 is a logic [0] no interrupt has occurred and D6 : D0 report real-time status. 2. The first SPI read after a 33689 reset returns the BATFAIL status flag bit D4.
SPI Register: Write Control Bits LINSL2 and LINSL1 -- LIN Baud Rate and Low-Power Mode Pre-Selection Bits These bits select the LIN slew rate and requested lowpower mode in accordance with Table 3. Reset clears the LINSL2 : 1 bits. Table 3. LIN Slew Rate Control and Device Low Power Mode Pre-Selection Bits (D7 and D6)
LINSL2 0 LINSL1 0 Description LIN slew rate normal (baud rate up to 20 kbps) LIN slew rate slow (baud rate up to 10 kbps) LIN slew rate fast (for program download, baud rate up to 100 kbps) Low power mode (Sleep or Stop mode) request, no change in LIN slew rate
0
1
1
0
1
1
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
LIN-PU -- LIN Pullup Enable Bit This bit controls the LIN pullup resistor during Sleep and Stop modes in accordance with Table 4. Reset clears the LIN-PU bit. Table 4. LIN Pullup Termination Control Bit (D5)
LIN-PU 0 1 Description 30 k pullup connected in Sleep and Stop mode 30 k pullup disconnected in Sleep and Stop mode
HS3: HS1 -- High-Side H3 : HS1 Enable Bits These bits enable the HS3 : HS1 bits in accordance with Table 5. Reset clears the HSx bit. Note If no PWM on HS1 and HS2 is required, the IN pin must be connected to the VDD pin. Table 5. High-Side Switches Control Bits (D4, D3, and D2)
HS3 0 1 Description HS3 OFF HS3 ON HS2 0 1 Description HS2 OFF HS2 ON (if IN = 1) HS1 0 1 Description HS1 OFF HS1 ON (if IN = 1)
MODE2 and MODE1 -- Mode Section Bits The MODE2 and MODE1 bits control the 33689 operating modes in accordance with Table 6. Table 6. Mode Control Bits (D1 and D0)
MODE2 0 0 1 1 MODE1 0 1 0 1 Description Sleep mode (3) Stop mode
To safely enter Sleep or Stop mode and to ensure that these modes are not affected by noise issue during SPI transmission, the Sleep / Stop commands require two SPI transmissions. Sleep Mode Sequence The Sleep command, as shown in Table 7, must be sent twice. Table 7. Sleep Command Bits
LINSL2 LINSL1 LIN-PU HS3 HS2 HS1 MODE2 MODE1
1 Normal mode + Watchdog clear (4) Normal mode
1
x
0
0
0
0
0
x = Don't care.
Notes 3. Special SPI command and sequence is implemented in order to avoid going into Sleep or Stop mode with a single 8-bit SPI command. Refer to Tables 7 and 8. 4. When a logic [0] is written to MODE1 bit while MODE2 bit is written as a logic [1]. After the SPI command is completed, MODE1 bit is set to logic [1] and the 33689 stays in Normal mode. In order to set the 33689 in Sleep mode, both MODE1 and MODE2 bits must be written in the same 8-bit SPI command. The Watchdog clear on Normal Request mode (150 ms) has no window.
Stop Mode Sequence The Stop command, as shown in Table 8, must be sent twice. Table 8. Stop Command Bits
LINSL2 LINSL1 LIN-PU HS3 HS2 HS1 MODE2 MODE1
1
1
x
0
0
0
0
1
x = Don't care.
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FUNCTIONAL DESCRIPTION FUNCTIONAL DEVICE OPERATION
SPI Register: Read Control Bits INTSCR -- Register Content Flags or Interrupt Source The INTSCR bit, as shown in Table 9, indicates if the register contents reflect the flags or an interrupt / wake-up source. Table 9. Interrupt Status (D7)
INTSCR 0 1 Description SPI word read reflects the flag state SPI word read reflects the interrupt or wake-up source
LINWU / LINFAIL -- LIN Bus Status Flag Bit This bit indicates a LIN wake-up condition or a LIN overcurrent/overtemperature in accordance with Table 10. Table 10. LIN Bus Status (D6)
LINWU/ LINFAIL 0 1 Description No LIN bus wake-up or failure LIN bus wake-up occurred or LIN overcurrent / overtemperature
VSOV -- Overvoltage Flag Bit, VSUV / BATFAIL -- Undervoltage Flag Bit, VDDT -- VDD Voltage Regulator Status Flag Bit, and HSST -- High-Side Status Flag Bit Table 11 indicates the register contents of the following flags: * VSOV flag is set on an overvoltage condition. * VSUV/BATFAIL flag is set on an undervoltage condition. * VDDT flag is set as pre-warning in case of an overtemperature condition on the voltage regulator. * HSST flag is set on overtemperature conditions on one of the high-side outputs. Table 11. Over- and Undervoltage, VDD Voltage Regulator, and High-Side Status Flag Bits (D5, D4, D3, and D2)
VSOV 0 Description VSUP below 19 V VSUV/ BATFAIL 0 Description VSUP above 6.0 V VDDT 0 Description No overtemperature HSST 0 Description HS No overtemperature HS1, HS2, or HS3 OFF (overtemperature)
1
VSUP above 18 V
1
VSUP below 6.0 V
1
VDD overtemperature pre-warning
1
L2 and L1 -- Wake-Up Inputs L2 and L1 Status Flag Bit The L2 and L1 flags, as shown in Table 12, reflect the status of the L2 and L1 input pins and indicate the wake-up source. Table 12. Switch Input Wake-Up and Real Time Status (D1 and D0)
L2 0 1 Description L2 input LOW L2 input HIGH or wake-up by L2 (first register read after wake-up) L1 0 1 Description L1 input LOW L1 input HIGH or wake-up by L1 (first register read after wake-up)
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
The 33689 can be configured in several applications. Figure 3 shows the 33689 in the typical master node application.
33689
VDD1
C4 C3 VDD
RST
VBAT VS1 C2 C1 D1
5.0 V/50 mA
Voltage Regulator
Reset Control
WDC
R1 IN MOSI MISO SCLK
CS INT
Window Watchdog
VS2
HS1
SPI and Mode Control
HS2 Pre-Driver
HS3 L2 C5 R6 R7
VDD1
VCC
MCU
EXT INPUT
ER2 R3 C7 R4 OUT TXD RXD LIN Physical Interface VS1 LIN C6 AGND TGND GND R8(1) E+ Current Sense Op Amp
L1 D2 R5 L1(1) LIN Bus
Component Values C1=47 F C2=C4=C5=100 nF C3=10 F C6=220 pF C7=4.7 nF
R1=33 k R2 and R3 depend on the application R4>5.0 k R5=1.0 k R6= 10 k R7=2.2 k R8=Varistor type TDK AVR-M1608C270MBAAB(1) L1 = SMD Ferrite Bead-Type TDK MMZ2012Y202B(1)
Notes: 1. L1 and R8 are external components to improve EMC and ESD performances. 2. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While freescale offers component recommendations in this configuration, it is the customer's responsibility to validate their application.
Figure 3. 33689 in Typical Master Node Application
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PACKAGING PACKAGING DIMENSIONS
PACKAGING
PACKAGING DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the 98A drawing number below.
DWB SUFFIX EW SUFFIX (Pb-FREE) 32-PIN SOIC WIDE BODY PLASTIC PACKAGE 98ARH99137A ISSUE B
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PACKAGING PACKAGING DIMENSIONS (CONTINUED)
PACKAGING DIMENSIONS (CONTINUED)
DWB SUFFIX EW SUFFIX (Pb-FREE) 32-PIN SOIC WIDE BODY PLASTIC PACKAGE 98ARH99137A ISSUE B
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REVISION HISTORY
REVISION HISTORY
REVISION 6.0
DATE 6/2006
DESCRIPTION OF CHANGES * * * * * * Implemented Revision History page Updated Outline Drawing to Revision "B" Eliminated all pages (pages 30 to 47) referring to the MC33689DWB/R2 device Removed MC33689DWB/R2 from the orderable parts information Updated to the prevailing form and style Removed MC33689DEW/R2 and replaced with MCZ33689DEW/R2 in the Ordering Information block
7.0
8/2006
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How to Reach Us:
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MC33689 Rev. 7.0 8/2006

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